Downloading Setup File

Choosing Installation Settings

Adding License

Agenda

Design Flow Steps P2

Design Flow Steps P1

Fundamentals Project Types

Design Flow Steps P3

Fundamentals P3 How to update Hardware Platform P1

Fundamentals P3 How to update Hardware Platform P2

Fundamentals P3 Useful files in Project Directory

Fundamentals P2 Flow Navigator

Different Reporting Mechanism

TCL Script for automation

Fundamentals of XIL Drivers P1

Fundamentals of XIL Drivers P2

Fundamentals of XIL Drivers P3

Writing Data to GPIO P2

Writing Data to GPIO P1

Reading Data from GPIO P1

Writing Data to GPIO P3

Reading Data from GPIO P2

Using Dual Channel of GPIO P1

Multiple Instances of GPIO P1

Using Dual Channel of GPIO P2

Multiple Instances of GPIO P2

Sending Data to UART P1

Receiving Data from UART

Multiple Instance of UARTLITE P1

Sending Data to UART P2

Working with UART16550 P1

Multiple Instance of UARTLITE P2

Working with UART16550 P2

How we observe the Current Count Value

Using Auto Reload Mode

Using both Timers

Using AXI Timer P2

Using PWM 50% Duty Cycle P2

Using PWM 50% Duty Cycle P1

Varying Duty Cycle

Fading Effect

Using PWM 50% Duty Cycle P3

AXI Timebase Watchdog Timer P1

Mulitple Event with WDT

AXI Timebase Watchdog Timer P2

Profile with AXI Timer P1

SDK Profiler P1

Profile with AXI Timer P2

SDK Profiler P2

Understanding Byte Addressable and Word Addressable

Adding BRAM IP to Block Design

BRAM Transactions using XIL IO Drivers

BRAM Transactions using pointers

Hardware Debugging Integrated Logic Analyzer P1

Hardware Debugging Integrated Logic Analyzer P3

Hardware Debugging Integrated Logic Analyzer P2

Software Debugging Serial Window

Interrupt with GPIO P1

AXI Timer Interrupt P1

AXI Timer Interrupt P2

Interrupt with GPIO P2

Interrupt with WDT P1

Interrupt with WDT P2

Reset with WDT

Create SLAVE AXI LITE Interface P1

Adding Port to Slave AXI LITE Interface P2

Create SLAVE AXI LITE Interface P2

Adding Port to Slave AXI LITE Interface P1

Create AXI Stream Interface P2

Adding Port to Slave AXI LITE Interface P3

Create AXI Stream Interface P1